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Scaling ion traps for quantum computing

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dc.contributor.author Uys, H
dc.contributor.author Amini, JM
dc.contributor.author Wesenberg, JH
dc.contributor.author Seidelin, S
dc.contributor.author Britton, J
dc.contributor.author Bollinger, JJ
dc.contributor.author Leibfried, D
dc.contributor.author Ospelkaus, C
dc.contributor.author Van Deventer, AP
dc.contributor.author Wineland, DJ
dc.date.accessioned 2011-01-21T08:18:55Z
dc.date.available 2011-01-21T08:18:55Z
dc.date.issued 2010-09
dc.identifier.citation Uys, H, Amini, JM, Wesenberg, JH et al. 2010. Scaling ion traps for quantum computing. 55th Annual Conference of the South African Institute of Physics (SAIP), CSIR International Convention Centre, Pretoria, 27 September-1 October 2010 en
dc.identifier.uri http://hdl.handle.net/10204/4785
dc.description 55th Annual Conference of the South African Institute of Physics (SAIP), CSIR International Convention Centre, Pretoria, 27 September-1 October 2010 en
dc.description.abstract The design, fabrication and preliminary testing of a chipscale, multi-zone, surface electrode ion trap is reported. The modular design and fabrication techniques used are anticipated to advance scalability of ion trap quantum computing architectures en
dc.language.iso en en
dc.publisher SAIP 2010 en
dc.relation.ispartofseries Conference Paper en
dc.subject Ion traps en
dc.subject Computing architectures en
dc.subject Quantum computing en
dc.subject SAIP Conference 2010 en
dc.title Scaling ion traps for quantum computing en
dc.type Conference Presentation en
dc.identifier.apacitation Uys, H., Amini, J., Wesenberg, J., Seidelin, S., Britton, J., Bollinger, J., ... Wineland, D. (2010). Scaling ion traps for quantum computing. SAIP 2010. http://hdl.handle.net/10204/4785 en_ZA
dc.identifier.chicagocitation Uys, H, JM Amini, JH Wesenberg, S Seidelin, J Britton, JJ Bollinger, D Leibfried, C Ospelkaus, AP Van Deventer, and DJ Wineland. "Scaling ion traps for quantum computing." (2010): http://hdl.handle.net/10204/4785 en_ZA
dc.identifier.vancouvercitation Uys H, Amini J, Wesenberg J, Seidelin S, Britton J, Bollinger J, et al, Scaling ion traps for quantum computing; SAIP 2010; 2010. http://hdl.handle.net/10204/4785 . en_ZA
dc.identifier.ris TY - Conference Presentation AU - Uys, H AU - Amini, JM AU - Wesenberg, JH AU - Seidelin, S AU - Britton, J AU - Bollinger, JJ AU - Leibfried, D AU - Ospelkaus, C AU - Van Deventer, AP AU - Wineland, DJ AB - The design, fabrication and preliminary testing of a chipscale, multi-zone, surface electrode ion trap is reported. The modular design and fabrication techniques used are anticipated to advance scalability of ion trap quantum computing architectures DA - 2010-09 DB - ResearchSpace DP - CSIR KW - Ion traps KW - Computing architectures KW - Quantum computing KW - SAIP Conference 2010 LK - https://researchspace.csir.co.za PY - 2010 T1 - Scaling ion traps for quantum computing TI - Scaling ion traps for quantum computing UR - http://hdl.handle.net/10204/4785 ER - en_ZA


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